OUTPUT IMPEDANCE ANALYSIS OF BUCK CONVERTER

 

Close loop Output impedance of the system will be depending on the loop of the system at lower frequency gain of the system will be more result in close loop output impedance will be decreases but in the case of higher frequency gain of system will be decreases results in close loop output impedance will be increases with increases the frequency.

 Fig. 11. Block diagram of Buck converter with Output impedance

 

Where K(s) is the loop gains of the system ZoL Impedance of Open loop the system Zocl is the closed-loop Impedance of Close loop the system. At high frequency gain of the system will be decreases nearly close to K(s)=0

Z_ocl = Zo_L

Buck converter has an output filter which are inductor (L) and capacitor(C), thus it will be formed primary LC filter, long trace created between converter output point and actual load point due to this parasitic inductance will come in picture which is (Lo1 & Lo2) and parasitic capacitance will be very small which is (Co) thus parasitic capacitor & inductor formed secondary LC filter.

The results of output impedance affect the voltage peak to peak variation during a Load transient event in two different case

 (1) Higher capacitance close to voltage regulator

 (2) Higher capacitance close to actual load side

(1) OUTPUT IMPEDANCE AT HIGHER CAPACITANCE CLOSE TO VOLTAGE REGULATOR

Fig. 13. Small signal model of Buck converter of with High Capacitor close to Voltage Regulator

 

Let us assume ESR & inductor DC resistance are neglected, to find out output impedance input voltage and duty cycle should be zero then output Impedance become

 

Z_ovr=

Primary resonance frequency (ωp_vr) =

Secondary resonance frequency(ωs_vr) =

Assume Parasitic capacitor very small Co= 0 then secondary resonance frequency will be very high because of Lo is also very small. Secondary resonance frequency will be

(ωs_vr) =

In this case peaking of output impedance will be significant at secondary resonance frequency.

(1)    Output impedance at higher capacitance close to actual load

Fig. 14. Small signal model of Buck converter of with High Capacitor close to actual load

Let us assume ESR & inductor DC resistance are neglected, to find out the output impedance input voltage and duty cycle should be zero then output impedance become

Z_oL=

Primary resonance frequency(ωp_L) =

Secondary resonance frequency (ωs_L) =

Assume Parasitic capacitor very small Co = 0 then secondary resonance frequency will be nearly close to primary resonance frequency.

Secondary resonance frequency(ωs_L) =

In this case peaking of output impedance will not be significant at secondary resonance frequency.

                                                                                                                                  I.            SIMULATION AND RESULT

Simulation test setup	Unit	Simulation test conditions	Unit
Output inductance(L)	100nH & (Rdc=400µΩ)	Input voltage	12V
Output capacitors(C)	276µF	Output voltage	1.8V
Higher capacitors(C1)	470×2µF	Fsw	1100kHz
Parasitic inductance Lo	10nH & (Rdc=50µΩ)	Load Step	20 to 30A
Parasitic capacitors (Co)	50pF	Load rate Fsw &Duty	1kHz , 50

 

Table. 2. Simulation test setup and condition for transient

 

 

Whenever we are using buck converter in server application we need low voltage and high current. Due to high current application Output impedance play important role in load transient, if output impedance is high then undershoot will be also high results in peak to peak ripple will be high if ripple will be high then for server application will not accept this ripple voltage result in server will be stop now. The results of output impedance affect the voltage peak to peak variation during a Load transient.