Switch Node Jitter Minimization in Synchronous buck converter

 

Modern systems such as AI applications need a fast load transient and high current for these servers to support these requirements high power buck converter is used. It has been demonstrated that a higher bandwidth is desirable for achieving a given transient requirement with a reduced capacitor size [3]. In this high current application, the parasitic inductance and capacitance will affect the load transient Therefore, we need to reduce the effect of parasitic inductance and capacitance to improve the load transient by optimization of output capacitor placement. But when we are increases the bandwidth one Another problem is arises which is an increased on-time jitter at the switch node due to increased noise within the control loop. The jitter can be, causing cycle skipping & generating more harmonics in control loop result is controller not proper working and getting high output ripple and bad load transient. In this paper I have discussed and analysis the improvement of load transient without affecting the other parameters by optimization of output capacitor placement and also on-time jitter has been improvement by adding Zeros in control loop feedback. It is desirable to achieve a high bandwidth while maintaining low on-time jitter.

The rest of this paper is  as follows. Section I provides jitter and noise analysis of a Constant on time control of buck converter. Section III presents the noise and bandwidth simulation results. Section IV presents the measurement results. Discussions of the results are presented in Section V. The conclusions and future work are s

                                                                                                                                       I.     PWM DUTY CYCLE JITTER

                                                                                                                                            (a)

(b)

 

 Fig. 1. (a) Buck converter with voltage feedback loop (b) Waveform of PWM with jitter

The output voltage Vo has a ripple voltage, it is not constant which is caused by the switch mode power supply converter. Thus, the control signal Vc will also affected from this output ripple which is fed through feedback resistor.

  Vc = Vref + (Vref – Vo)

the jitter could be caused by the electromagnetic noise in control loop which is a periodic function. it can be decomposed into the sum of a set of sine and cosine functions. Also, sine wave as perturbation signal is produced the PWM jittering. Hence, control signal is discomposed in two signals first was dc value Vdc with perturbation signal Vp which has amplitude V_pmax and frequency fp. thus PWM signal consists jitter which is caused by perturbation signal. The Tjitter has been described below expression V_rampmax is the maximum value of ramp signal V_pmax is the maximum value of perturbation signal [2].

                                                                                                                              I.     JITTER AND NOISE ANALYSIS

Jitter is the small variation of the switching frequency or in other words it is the variation of percentage of duty cycle and caused by Noise in control loop.Effect of jitter was introducing fluctuations in the output voltage  may lead controller proper not working and  Reduces the efficiency due to unnecessary switching losses.As per fast constant on time control (FCOT) topology Should be less than 15%.

 Fig. 2. Block diagram of Constant on time control

 

It has fast constant on time control topology is used to generate the pulse for turn on the high side Mosfet, these controllers have ramp generator, Floor Amplifier, comparator and generator which generates the electronics noise in the control feedback loop which causes the jitter in switch node. there is a complex to analysis the noise in this system. let us consider referring all the noise to the output of the floor amplifier is Vn and assuming remaining components are noise-less[1]. Peak to peak Jitter is defined as.

Tjitter =

here there are two way to decrease the jitter first one is reduce the noise in control loop and second one is increase the amplitude of Vramp.

 Fig. 3. System diagram of a Constant on time control of buck converter

 

The block diagram of buck converter is drawn in Fig. 3, where Ge(s) is the transfer function of the floor amplifier, Gpl(s) is the control-to-output transfer function, and Gf(s) is the feedback factor of the resistor divider. the noise transfer function from the input to the output of the floor amplifier when the loop is closed. Let us consider the input-referred noise is Vn_in(s) and the floor amplifier output noise is Vn_c(s), then the noise transfer function can be found by

G_n(s) =   =

 

At lower frequency loop gain of the system will be large then approximate transfer function will be

G_n(s) =   =

       

Now at lower frequency it depends on the power stage and feedback loop gain if we are increasing these loop results in decrease the closed loop gain of  floor Amplifier consequence noise will be reduced and result in reduce the jitter.At higher frequency loop gain of the system will be decrease then close loop noise transfer function will be

G_n(s) =   =

 

G_n(s)= Ge(s)

In this case close loop noise transfer function will be equal to the open loop gain of the Floor.For higher loop bandwidth and lower jitter, we need to add another zero into the system and should be before the cross over frequency which is attenuate more higher frequency noise at lower frequency. Another zero we can be introduced in three places Floor Amplifier, Power stage and feedback. If introduce extra zero in floor Amplifier the it will increase high frequency noise and in case of power stage will introduced the ESR and ESL that’s Why extra zeros introduced in to the feedback of the system.

(a)

(b)

Fig.4. (a) Circuit diagram of Buck converter without voltage feedforward capacitor(b) With feedforward Capacitor

 

Without feedforward capacitor the output voltage to feedback voltage transfer function will be

 =

With feedforward capacitor the output voltage to feedback voltage transfer function will be

       =   ×

 = ×Gff(s)

 

Gff(s) =

f_z = 

f_p  = 

 

 

(a)

(b)

Fig.5. (a) Bode plot of Buck converter without voltage feedforward capacitor(b) With feedforward Capacitor

Gff(s) is the additional transfer function due to feedforward capacitor in this case this term defined add one zero one pole which is boost the phase of the system between zero and pole frequency and also increased the gain of the system after zero frequency which is reduce the gain of noise closed loop floor Amplifier result is jitter will be reduced [1].

                                                                                                                                      II. Measurement and results

In this process evaluation board shown in below figure which is High power buck converter and it is configured for 1.8 output voltage by tuning the feedback divider resistance Rfb1=20kΩ and Rfb2=10kΩ

The switch node jitter was measured at no load using a Tektronix  5 series Mixed signal oscilloscope with infinite persistence time  are measured and it was  presented in Fig. 9

Fig.6. Evaluation board of High-power buck converter

 

Test setup and conditions are taken as per below given in matrix.

      Table. 1 Test setup and conditions for jitter

 

Test setup	Unit	Test conditions	Unit
Output inductance(L)	100nH & (Rdc=400µΩ)	Input voltage	12V
Output capacitors(C)	47×20µF +22 µF×8=1028 µF	Output voltage	1.8V
Feedforward capacitors (Cff)	220pF	Fsw	1100kHz

 

With type-III Compensator

Fig.7.Waveform of Switch node voltage jitter without feedforward Capacitor

Jitter (%) =×100

Jitter (%) =×100

Jitter (%) = 21.37%

        With type-III Compensator and Feedforward Capacitor

  Fig.8. Waveform of Switch node voltage jitter with feedforward Capacitor

Jitter (%) =×100

Jitter (%) =×100

             = 4.66%

In both cases have measured the jitter but with feedforward capacitor of type-III compensator is the 4.66 % which is less than 21.37 % jitter with type-III compensator.